Architecture Design Exploration

Define Optimal Macro and Micro Architecture

Complex design challenges characterized by shrinking geometry, functionality within both the hardware and software domains, and strict requirements for performance and power efficiency driven by the designated application, are changing how systems are being designed. In the consumer markets, user's experience is a key for product success. It is determined by the performance of the combined hardware and software application. To achieve an optimal architecture and allow design scalability, design engineers must maintain visibility over the power and performance requirements ahead of production when the greatest impact on design implementation is still possible.

Architecture Validation

Enable Hardware and Software Verification Early in the Design Cycle

System verification challenges have gone beyond the scope of what RTL can address. Abstracting hardware modeling and moving it earlier in the development process enables faster validation and debug of both the hardware and the software components of the system. SystemC and the Transaction Level Modeling (TLM) 2.0 communication standards enable system-wide verification and hardware software integration much earlier in the design cycle.

Vista Virtual Prototyping for SystemC / TLM 2.0 and QEMU

Integrate and Optimize Software with Early Hardware Models

With software development becoming the fastest growing component of NRE costs for both SoC and final product development, the challenges of developing, integrating, validating, and optimizing software in the context of hardware are dominating the embedded design process. Thus it has become a necessity to make a fast, accurate, and low-cost simulation model of the hardware available early to the embedded software team. Vista™ Virtual Prototyping provides an early abstract SystemC / TLM 2.0 and QEMU functional model of the hardware to software engineers even before the hardware design is implemented in RTL. It can run software on embedded processor models at speeds on-par with actual hardware. Vista Virtual Prototyping is seamlessly integrated with Sourcery™ CodeBench Virtual Edition to provide additional capabilities and benefits, such as the visibility and control to debug complex software/hardware interactions and the ability to optimize the software to meet final product performance and power goals.

Methodologies for Functional Verification

Verification Methodologies form the backbone of a solid verification strategy. Mentor Graphics is actively driving advanced methodologies and their standardization across the industry.

• • Assertion Based Verification
  Assertion-based verification (ABV) is a methodology in which designers use assertions to capture specific design intent and, either through simulation, formal verification, or emulation of these assertions, verify that the design correctly implements that intent.


• • Universal Verification Methodology
  The UVM is the first Industry-Standard verification methodology delivering an open and unified class library and methodology for interoperable verification IP and testbenches. Based on OVM and written in SystemVerilog 1800, the UVM is the culmination of collaboration among user and vendor companies in Accellera.


• • Processor-Driven Verification
  Current techniques of applying test vectors from an HDL testbench only begin to mimic processor bus behavior. The introduction of processor-driven test benches into the existing verification methodology enables real-world verification and extensive reuse of testbench software throughout the project.

Mentor Verification IP

Comprehensive verification IP built using advanced methodologies for fastest time to verification sign-off.

Today's designs rely heavily on a growing variety of complex industry standard interfaces that must be verified to ensure IP interoperability and system behavior. Mentor's verification IP (VIP) improves quality and reduces schedule times by building Mentor's protocol and methodology expertise into a library of reusable components that support many industry standard interfaces. This frees up engineering resources from having to spend time developing BFMs, verification components, or VIP themselves, enabling them to focus on the unique and high-value aspects of their design.
Mentor's VIP integrates seamlessly into advanced verification environments, including testbenches built using UVM, OVM, Verilog, VHDL, and SystemC. It is the industry's only VIP with a native SystemVerilog UVM and OVM architecture across all protocols, ensuring maximum productivity and flexibility.
Combined with the Questa Verification Platform, complete VIP components reduce bring up time and enable rapid coverage closure. Comprehensive protocol assertions allow Questa Formal users to exhaustively prove design correctness, while support for Veloce Emulation Systems enables users to easily transition to high-performance simulation acceleration for orders-of-magnitude gains in throughput.

Advanced SoC Debug Solution

Intuitive and powerful HW and SW debug solutions to improve debug productivity across ESL, formal, RTL/gate-level simulation and emulation platforms

The Mentor debug solution maximizes performance, capacity and automation for the complete SoC design and verification cycle. Tightly integrated with Questa Simulation and Veloce Emulation, the solution includes the industry-leading Codelink product family for hardware and software debug, and the new Visualizer Debug Environment for testbench and hardware debug..

Requirements Tracking

Clearly tracking hardware implementation for specified requirement validation has become a preferred development practice that is well suited for safety critical projects in medical, transportation, aerospace and military, but is equally significant for any complex ASIC or FPGA design.

Design Creation

Whether designing an FPGA or ASIC, the devices have advanced capabilities and complex features that, when put under tight development cycles, burden the design teams to produce efficient and robust chips. Hence, the design teams have placed more demands on HDL processes, automation, and style guidelines for developing quality design results.

Design Reuse

Effective design reuse is a critical objective for every electronic design company as 75% of future productivity gains will come through reuse. Executives, managers, and engineers all have a big stake in reuse, but nearly everyone underestimates the challenges associated with it.

Advanced FPGA Synthesis

Precision Synthesis offers high quality of results, industry-unique features, and integration across Mentor Graphics' FPGA Flow– the industry's most comprehensive FPGA vendor independent solution.

ASIC Prototyping

With increasing competitive pressures and shorter product life cycles, designers have less time to develop high performance and complex ASIC designs.

SystemVerilog Design & Synthesis

SystemVerilog is a powerful language that enables tremendous improvements in both advanced design and verification methodologies. However, to fully leverage the language, design and verification engineers need to become familiar with:

• ✔ Object Oriented Programming Techniques
• ✔ Methods for integrating existing VHDL and Verilog code
• ✔ New constructs that enable coding at higher levels of abstraction

FPGA Verification

Precision Synthesis offers high quality of results, industry-unique features, and integration across Mentor Graphics' FPGA Flow– the industry's most comprehensive FPGA vendor independent solution.

Calibre Real Time

On-Demand Calibre signoff verification. Calibre® RealTime enables on-demand Calibre signoff design rule checking (DRC) for custom and analog/mixed-signal design flows, improving both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance.

The award-winning Calibre RealTime platform completely transforms the custom/analog layout-verification-simulation loop by bringing Calibre signoff verification into the design creation process.

Olympus-SoC

The Olympus-SoC™ physical implementation platform meets the challenges of manufacturability and low-power for IC designs at advanced nodes. Olympus-SoC delivers high quality layouts, fast turnaround, and rapid closure.

USB

USB is a commonly deployed digital wired interface on PCs, printers, digital cameras, PDAs, and other digital consumer electronic products.

USB subsystem

The goal of Mentor' Graphic's IP Division is to offer a complete IP subsystem available in the standards-based connectivity space.

Ethernet

With the Networking industry's ever-increasing demand for faster speeds, we are committed to providing the most flexible and problem-free IP cores for Ethernet connectivity.

Mixed Signal

All of our Mixed Signal IP cores include Mentor Graphics 5-STAR global customer support for quicker response times, and ultimately a faster time to market for your end products.

Storage

We are the only Storage IP vendor to offer non-standard clocking support for our customer's Parallel ATA designs, which provide greater flexibility when integrating PATA Host controller.

Peripheral

Peripheral IP is often required to complete ASIC or SoC designs. It ranges in type and complexity from microcontrollers to communication interfaces such as I2C.

Memory-IP

For designs requiring embedded Memory IP with the concurrent delivery of the highest possible density at the lowest possible dynamic power, leakage and cost while achieving target speed.

Calibre Computational Lithography

Low k1 photolithography processes are driving up the complexity and data volume of RET applications in nanometer designs. At 45nm and beyond, more complex models and through-process-window correction and verification requirements significantly increase computational burden. Both the lithographic challenges and the computational complexity associated with the advanced process nodes create a need for advanced capabilities in computational lithography software and hardware.

Calibre Mask Process Correction

The next few IC technology nodes will be more challenging than any other transition since the first integrated circuit. Until the 32 nm node, distortions involved in making the masks using 193 nm lithography were small and had little impact since mask features are four times larger than the actual features on a die. Traditional OPC has mainly addressed the wafer image transfer and only included mask making effects as a part of the overall OPC model.

Calibre Mask Data Preparation

Mentor's Mask Data Preparation (MDP) solution is fully compatible with the Calibre platform, enabling you to complete all resolution enhancement processing and mask data format conversion tasks in one mask fabrication batch run using a single control language.

Calibre MDP provides Layer derivation Mirroring Scaling Rotation Planarization fill Global and selective sizing Hierarchical mask rule checking (MRC) Mask proximity correction (MPC) Mask fracturing into many standard output formats Calibre MDP provides direct output for the leading mask writer formats in the sub-wavelength era, such as MEBES, JEOL, Micronic, and Variable-Shaped-Beam, in addition to standard GDSII.

Xpedition™ Enterprise

Xpedition™ Enterprise from Mentor Graphics is the industry's most innovative PCB design flow, providing integration from system design definition to manufacturing execution. Its unique, patented technologies can reduce design cycles by 50 percent or more while significantly improving overall quality and resource efficiency.

The Xpedition Enterprise advantage
Xpedition Enterprise delivers a complete portfolio of best-in-class solutions for engineering, design, analysis, manufacturing, and data management including:

• • Full data integrity throughout the entire design and IP management process
• • Flow-wide concurrent engineering
• • Correct-by-design methodology and flow automation
• • Virtual prototyping
• • Integrated design-for-manufacturing

HyperLynx

HyperLynx® offers a complete suite of analysis and verification software that meets the needs of PCB engineers at any point in the board design flow.
Easy to use and integrate into your flow, HyperLynx equips PCB engineers to efficiently analyze, solve and verify critical requirements to avoid costly re-spins. Achieve greater innovation, faster time-to-market and decreased costs with HyperLynx.

PADS

Start using PADS in minutes—without downloading and installing software. Our online PADS virtual lab gives you the complete PADS experience and workflow immediately.

• • Schematic capture
• • Pre- and post-route signal integrity analysis
• • PCB layout and routing

Logic Test

The industry's most powerful suite of logic test solutions

Advanced design techniques are used in creating the logic portions of SoCs, presenting significant challenges to achieving high-quality silicon test. To meet these challenges, Mentor Graphics offers the industry's most powerful suite of logic test solutions.

These solutions have more than a decade, and thousands of tape-outs, of successful high-quality test using both compression and vectorless approaches. Together, they provide maximum flexibility for achieving the most effective test time versus quality optimization.

The Tessent® logic test solutions also provide unique support for reduced pin count testing, extensive support for testing low-power designs as well as advanced fault models like Cell-Aware.

Products:

• • Tessent BoundaryScan
• • Tessent LogicBIST
• • Tessent FastScan
• • Tessent IJTAG
• • Tessent Scan
• • Tessent SoCScan
• • Tessent TestKompress

Memory Test

Advanced memory self-test and repair capabilities

Tessent® memory test solutions provide the industry's most advanced memory self-test and repair capabilities. Key features include comprehensive test and diagnostic capabilities to address the quality requirements of new process nodes and memory designs as well as comprehensive repair analysis and self-repair capabilities. Tessent memory test solutions also provide advanced design automation to ensure that all necessary embedded test and repair capabilities can be integrated quickly and efficiently into the design. This is key as the number of memories continues to grow. Tessent memory test solutions support ICs of any size or complexity, reducing IC engineering development effort and improving time-to-market.

Mixed-Signal Test

Minimize tester hardware requirements and reduce tests costs

The Tessent™ mixed-signal test solutions are vendor- and ATE-independent, addressing the growing number of SerDes interfaces and PLLs on today's SoC designs. Characterization with PC plus GPIB-controlled benchtop equipment reduces tester hardware requirements, and the microWire-controlled clock conditioner PLL shortens your time-to-market. Tessent SerdesTest and Tessent PLLTest minimize tester hardware requirements and reduce tests costs.

Silicon Learning

Increase productivity during validation and yield ramp phases

The Tessent® silicon learning products increase productivity during critical silicon validation and yield ramp phases. The products provide solutions for test bring-up, silicon characterization, diagnosis-driven yield analysis, and failure analysis. Specialized statistical analysis eliminates diagnosis noise and accelerates the time to root cause of yield loss.

Volcano Vehicle Systems Architect (VSA)

Volcano Vehicle System Architect (VSA) is a systems design tool for AUTOSAR-based systems. It enables engineers to design automotive SW and HW architectures and to manage the relationships between the two. At the same time, it provides the user with required support to manage industrial-scale projects with distributed development partners.

These solutions have more than a decade, and thousands of tape-outs, of successful high-quality test using both compression and vectorless approaches. Together, they provide maximum flexibility for achieving the most effective test time versus quality optimization.

The Tessent® logic test solutions also provide unique support for reduced pin count testing, extensive support for testing low-power designs as well as advanced fault models like Cell-Aware.

Products:

• • Tessent BoundaryScan
• • Tessent LogicBIST
• • Tessent FastScan
• • Tessent IJTAG
• • Tessent Scan
• • Tessent SoCScan
• • Tessent TestKompress

Volcano VSTAR

Volcano™ VSTAR AUTOSAR Basic Software (BSW) stack provides a fully AUTOSAR 4.0 compliant and scalable middleware for ECU design which abstracts the application from the HW-dependent layer. It is supported by a complete top-down development tool suite.

VSTAR includes:

• • Operating system
• • Run-time environment (RTE) Generator
• • Modules for mode management
• • Modules for memory management, diagnostic and communication services
• • I/O hardware abstraction firmware
• • Optional communication stacks for LIN, CAN and FlexRay

Volcano Network Architect (VNA)

Volcano Network Architect (VNA) is a CAN and LIN communication design tool that supports system engineering development processes. VNA is a standalone tool suitable for integration in legacy design processes, as well as the ideal foundation for building a system engineering-based communication design process. VNA connects easily to other tools, e.g., enterprise-wide communication databases.

Valor MSS Solutions

• • Make or Buy
• • Rapid Time to Market
• • On-Time Every Time
• • Reduce Waste
• • Eliminate Excess Inventory
• • Process Conformance
• • Tracability for Quality
• • Action Through Visibility

Valor MSS Modules

• • Valor MSS Foundation
• • Valor MSS Process Preparation
• • Valor MSS Production Planning
• • Valor Parts Library (VPL)
• • Valor MSS Asset Utilization
• • Valor MSS Material Verification
• • Valor MSS Material Management
• • Valor MSS Material Traceability
• • Valor MSS Quality Management
• • Valor MSS Business Intelligence

SystemVision Multi-Discipline Development Environment

From conceptual design exploration through detailed implementation, SystemVision is a single design exploration and optimization environment supporting powerful verification and analysis capabilities for challenging multi-discipline designs.

Using SystemVision you can explore concepts, validate performance specifications, investigate architectural partitions, and integrate abstract or implementation-level electronics, sensors/actuators, controls, and embedded software, all in a single virtual environment. Utilizing the power of the IEEE standard VHDL-AMS modeling language, and supporting industry-standard SPICE modeling techniques, SystemVision offers reduced development time, simplified HW/SW integration, and reduced risk of late stage bugs that often jeopardize program success.

SystemVision – A Portfolio of Tools
SystemVision is a multi-discipline design exploration and analysis tool. SystemVision conneXion(SVX) extends SystemVision's multi-discipline capabilities by connecting multiple domain-specific tools and processes together in a single simulation environment. SVX connects design partitions executed in SystemVision, MathWorks Simulink, National Instruments LabVIEW, SystemC, C/C++, Java, and AUTOSAR over a secure, managed signal channel. SV CAN Network SI is a specialized SystemVision package aimed at CAN network designers who need to analyze the CAN bus physical layer and ensure optimized, lowest cost, error-free network architectures.

BridgePoint Comprehensive xtUML Tool Suite

BridgePoint offers a model-driven design environment utilizing the power of executable and translatable UML (xtUML). BridgePoint provides a modern alternative to legacy paper-based methods for capturing a system's conceptual design. Going beyond the traditional UML capabilities, BridgePoint adds extensions that turn the UML model into an executable specification and provide a direct translation path from UML to a target language and platform.

Mentor Graphics has placed its previously proprietary front-end UML editor into the open source domain. Accessible for free download from xtUML.org, this editor was formerly part of the company's powerful BridgePoint xtUML environment. Providing a free editor and releasing the editor code as an open source software project is designed to encourage the advancement of model-driven development within the system design community. xtUML.org provides the system design community with access to xtUML editing capabilities, along with a forum to advance the use of this methodology.

BridgePoint is based on the OMG UML standard. Mentor Graphics is a member of OMG and supports standards throughout the industry. OMG's modeling standards, including the Unified Modeling Language (UML) and Model Driven Architecture (MDA), enable powerful visual design, execution, and maintenance of software and other processes.

The BridgePoint Tool Set
BridgePoint is an advanced UML tool suite aimed at systems, software, and hardware engineers developing sophisticated embedded systems. Specifically designed to address the challenges of complex HW/SW interactions, BridgePoint's powerful xtUML approach supports UML execution and translation from UML to C, C++, SystemC, and AUTOSAR-compliant C (which can be run within Mentor's Vehicle Systems Integrator (VSI), alongside the Volcano VSx AUTOSAR tool suite. Model execution extends the traditional documentation aspects of UML, enabling early validation and demonstration of requirements. It also allows testing and verification of the system via a virtual prototype prior to physical prototyping. Model translation allows abstract, target-independent models and validation suites to transform into the specific design and test implementation (in software and/or hardware).